Power management integrated circuit

ABSTRACT

A power management integrated circuit (PMIC) is disclosed. The PMIC is configured to generate multiple voltages during a voltage generation period(s). In embodiments disclosed herein, the voltage generation period(s) is divided into multiple voltage generation intervals. A voltage generation circuit is configured to generate and maintain a respective one of the voltages during a respective one of the voltage generation intervals based on a reference voltage modulated for the respective one of the voltage generation intervals to thereby make the voltages concurrently available during the voltage generation period(s). Moreover, a voltage modulation circuit is configured to modulate the reference voltage in each of the voltage generation intervals based on a single direct-current to direct-current (DC-DC) power inductor. As a result, the PMIC can concurrently support multiple load circuits (e.g., power amplifiers) with significantly reduced footprint.

RELATED APPLICATIONS

This application claims the benefit of provisional patent applicationSer. No. 63/121,622, filed Dec. 4, 2020, the disclosure of which ishereby incorporated herein by reference in its entirety.

FIELD OF THE DISCLOSURE

The present disclosure is related to a power management integratedcircuit (PMIC).

BACKGROUND

Mobile communication devices have become increasingly common in currentsociety for providing wireless communication services. The prevalence ofthese mobile communication devices is driven in part by the manyfunctions that are now enabled on such devices. Increased processingcapabilities in such devices means that mobile communication deviceshave evolved from being pure communication tools into sophisticatedmobile multimedia centers that enable enhanced user experiences.

The redefined user experience requires higher data rates offered by suchadvanced wireless communication technologies as fifth-generationnew-radio (5G-NR). To achieve higher data rates, a mobile communicationdevice may employ a power amplifier(s) to amplify a radio frequency (RF)signal(s) (e.g., maintaining sufficient energy per bit) beforetransmission. Given that the power amplifier(s) requires a supplyvoltage(s) for operation, a power management integrated circuit (PMIC)is thus required to generate and provide the supply voltage(s) to thepower amplifier(s).

Given that the PMIC often needs to concurrently generate multiple supplyvoltages for multiple power amplifiers, the PMIC typically includesmultiple direct-current to direct-current (DC-DC) power inductors. As aresult, the PMIC can claim a larger portion of precious real estate inthe mobile communication device. Hence, it is desirable to reduce thenumber of DC-DC power inductors in the PMIC to help reduce footprint ofthe PMIC.

SUMMARY

Embodiments of the disclosure relate to a power management integratedcircuit (PMIC). The PMIC is configured to generate multiple voltagesduring a voltage generation period(s). In embodiments disclosed herein,the voltage generation period(s) is divided into multiple voltagegeneration intervals. A voltage generation circuit is configured togenerate and maintain a respective one of the voltages during arespective one of voltage generation intervals based on a referencevoltage modulated for the respective one of the voltage generationintervals to thereby make the voltages concurrently available during thevoltage generation period(s). Moreover, a voltage modulation circuit isconfigured to modulate the reference voltage in each of the voltagegeneration intervals based on a single direct-current to direct-current(DC-DC) power inductor. As a result, the PMIC can concurrently supportmultiple load circuits (e.g., power amplifiers) with significantlyreduced footprint.

In one aspect, a PMIC is provided. The PMIC includes a voltagegeneration circuit configured to generate and maintain a number ofvoltages during at least one voltage generation period based on areference voltage. The PMIC also includes a voltage modulation circuitconfigured to modulate the reference voltage during the at least onevoltage generation period. The PMIC also includes a control circuit. Thecontrol circuit is configured to divide the at least one voltagegeneration period into a number of voltage generation intervals forgenerating the number of voltages, respectively. The control circuit isalso configured to cause the voltage modulation circuit to modulate thereference voltage to a respective level during each of the number ofvoltage generation intervals. The control circuit is also configured tocause the voltage generation circuit to generate and maintain each ofthe number of voltages in a respective one of the number of voltagegeneration intervals based on the respective level of the referencevoltage modulated during the respective one of the number of voltagegeneration intervals.

Those skilled in the art will appreciate the scope of the presentdisclosure and realize additional aspects thereof after reading thefollowing detailed description of the preferred embodiments inassociation with the accompanying drawing figures.

BRIEF DESCRIPTION OF THE DRAWING FIGURES

The accompanying drawing figures incorporated in and forming a part ofthis specification illustrate several aspects of the disclosure, andtogether with the description serve to explain the principles of thedisclosure.

FIG. 1 is a schematic diagram of an exemplary power managementintegrated circuit (PMIC) configured according to embodiments of thepresent disclosure to concurrently generate multiple voltages withoutrequiring multiple direct-current to direct-current (DC-DC) powerinductors;

FIG. 2 is a schematic diagram providing an exemplary illustration of avoltage generation period during which the PMIC of FIG. 1 can beconfigured to concurrently generate the voltages;

FIG. 3 is a schematic diagram providing an exemplary illustration of avoltage modulation circuit provided in the PMIC of FIG. 1 and configuredaccording to an embodiment of the present disclosure to include a singleDC-DC power inductor;

FIG. 4 is a schematic diagram providing exemplary illustration of avoltage generation circuit provided in the PMIC of FIG. 1 and configuredaccording to an embodiment of the present disclosure to generate andmaintain the voltages;

FIGS. 5A and 5B are signal diagrams illustrating exemplary operations ofthe PMIC of FIG. 1 in accordance with embodiments of the presentdisclosure; and

FIG. 6 is a schematic diagram providing an exemplary illustration of avoltage generation circuit provided in the PMIC of FIG. 1 and configuredaccording to an alternative embodiment of the present disclosure.

DETAILED DESCRIPTION

The embodiments set forth below represent the necessary information toenable those skilled in the art to practice the embodiments andillustrate the best mode of practicing the embodiments. Upon reading thefollowing description in light of the accompanying drawing figures,those skilled in the art will understand the concepts of the disclosureand will recognize applications of these concepts not particularlyaddressed herein. It should be understood that these concepts andapplications fall within the scope of the disclosure and theaccompanying claims.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, these elements should notbe limited by these terms. These terms are only used to distinguish oneelement from another. For example, a first element could be termed asecond element, and, similarly, a second element could be termed a firstelement, without departing from the scope of the present disclosure. Asused herein, the term “and/or” includes any and all combinations of oneor more of the associated listed items.

It will be understood that when an element such as a layer, region, orsubstrate is referred to as being “on” or extending “onto” anotherelement, it can be directly on or extend directly onto the other elementor intervening elements may also be present. In contrast, when anelement is referred to as being “directly on” or extending “directlyonto” another element, there are no intervening elements present.Likewise, it will be understood that when an element such as a layer,region, or substrate is referred to as being “over” or extending “over”another element, it can be directly over or extend directly over theother element or intervening elements may also be present. In contrast,when an element is referred to as being “directly over” or extending“directly over” another element, there are no intervening elementspresent. It will also be understood that when an element is referred toas being “connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present.

Relative terms such as “below” or “above” or “upper” or “lower” or“horizontal” or “vertical” may be used herein to describe a relationshipof one element, layer, or region to another element, layer, or region asillustrated in the Figures. It will be understood that these terms andthose discussed above are intended to encompass different orientationsof the device in addition to the orientation depicted in the Figures.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the disclosure.As used herein, the singular forms “a,” “an,” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises,”“comprising,” “includes,” and/or “including” when used herein specifythe presence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this disclosure belongs. It willbe further understood that terms used herein should be interpreted ashaving a meaning that is consistent with their meaning in the context ofthis specification and the relevant art and will not be interpreted inan idealized or overly formal sense unless expressly so defined herein.

Embodiments are described herein with reference to a power managementintegrated circuit (PMIC). The PMIC is configured to generate multiplevoltages during a voltage generation period(s). In embodiments disclosedherein, the voltage generation period(s) is divided into multiplevoltage generation intervals. A voltage generation circuit is configuredto generate and maintain a respective one of the voltages during arespective one of voltage generation intervals based on a referencevoltage modulated for the respective one of the voltage generationintervals to thereby make the voltages concurrently available during thevoltage generation period(s). Moreover, a voltage modulation circuit isconfigured to modulate the reference voltage in each of the voltagegeneration intervals based on a single direct-current to direct-current(DC-DC) power inductor. As a result, the PMIC can concurrently supportmultiple load circuits (e.g., power amplifiers) with significantlyreduced footprint.

In this regard, FIG. 1 is a schematic diagram of an exemplary PMICconfigured according to embodiments of the present disclosure togenerate multiple voltages V_(CC1)-V_(CCN) without requiring multipleDC-DC power inductors. In an embodiment, the PMIC 10 is configured togenerate and maintain the voltages V_(CC1)-V_(CCN) during at least onevoltage generation period (T) as illustrated in FIG. 2 . FIG. 2 is aschematic diagram providing an exemplary illustration of the voltagegeneration period (T) during which the PMIC 10 of FIG. 1 can beconfigured to concurrently generate the voltages V_(CC1)-V_(CCN).

In a non-limiting example, the voltage generation period (T) can beequally divided into multiple time slots (Δt). Accordingly, multiplevoltage generation intervals dT₁-dT_(N) can be further defined to eachinclude a respective one or more of the time slots (Δt). Each of thevoltage generation intervals dT₁-dT_(N) can be longer if a respectiveone of the voltages V_(CC1)-V_(CCN) is higher or be shorter if arespective one of the voltages V_(CC1)-V_(CCN) is lower. For example,the voltage generation interval dT₁ can be configured to include twotime slots (2Δt) for generating a higher voltage V_(CC1). In contrast,the voltage generation intervals dT₂ and dT_(N) are configured to eachinclude one time slot (Δt) for generating lower voltages V_(CC2) andV_(CCN). Accordingly, the PMIC 10 can be configured to generate andmaintain each of the voltages V_(CC1)-V_(CCN) during a respective one ofthe voltage generation intervals dT₁-dT_(N). In this regard, the voltagegeneration intervals dT₁-dT_(N) appear to be

analogous to a time-division schedule for generating the voltagesV_(CC1)-V_(CCN).

However, as discussed in detail below, the PMIC 10 can be furtherconfigured to maintain each of the voltages V_(CC1)-V_(CCN) at arespective constant level during each of the voltage generationintervals dT₁-dT_(N). As such, despite that the voltages V_(CC1)-V_(CCN)are each generated in a time-division fashion, the PMIC 10 cannevertheless make the voltages V_(CC1)-V_(CCN) concurrently availableduring the voltage generation period (T). Accordingly, the voltagegeneration period (T) should be determined by taking into considerationas to how long the PMIC 10 can maintain the voltages V_(CC1)-V_(CCN) andto what degree a ripple can be tolerated in each of the voltagesV_(CC1)-V_(CC).

With reference back to FIG. 1 , the PMIC 10 includes a voltage

generation circuit 12 and a voltage modulation circuit 14. The voltagegeneration circuit 12 is configured to generate and maintain arespective one of the voltages V_(CC1)-V_(CCN) during a respective oneof voltage generation intervals dT₁-dT_(N) based on a reference voltageV_(REF) modulated for the respective one of the voltage generationintervals dT_(n)-dT_(N). The voltage modulation circuit 14 is configuredto modulate the reference voltage V_(REF) in each of the voltagegeneration intervals dT₁-dT_(N).

The PMIC 10 further includes a control circuit 16, which can be a fieldprogrammable gate array (FPGA), as an example. The control circuit 16 isconfigured to divide the voltage generation period (T) into the voltagegeneration intervals dT₁-dT_(N). Accordingly, the control circuit 16 canprovide a target signal 18 to cause the voltage modulation circuit 14 tomodulate the reference voltage V_(REF) to a respective level during eachof the voltage generation intervals dT₁-dT_(N). In addition, the controlcircuit 16 can assert multiple control voltages CTRL₁-CTR_(N) to therebycause the voltage generation circuit 12 to generate and maintain each ofthe voltages V_(CC1)-V_(CCN) in a respective one of the voltagegeneration intervals dT₁-dT_(N) based on the respective level of thereference voltage V_(REF) modulated during the respective one of thevoltage generation intervals dT₁-dT_(N). Herein, asserting the controlvoltages CTRL₁-CTR_(N) means increasing the control voltagesCTRL₁-CTR_(N) above respective threshold voltages. In contrast,de-asserting the control voltages CTRL₁-CTR_(N) means decreasing thecontrol voltages CTRL₁-CTR_(N) below the respective threshold voltages.

Given that the voltages V_(CC1)-V_(CCN) are each generated in atime-division fashion, the voltage modulation circuit 14 can alsomodulate the reference voltage V_(REF) in the time-division fashion. Assuch, it is not necessary for the voltage modulation circuit 14 toconcurrently modulate the reference voltage V_(REF) in the voltagegeneration intervals dT₁-dT_(N), thus making it possible for the voltagemodulation circuit 14 to operate based on a single DC-DC power inductorto help reduce footprint of the PMIC 10.

In this regard, FIG. 3 is a schematic diagram providing an exemplaryillustration of the voltage modulation circuit 14 in the PMIC 10 of FIG.1 configured according to an embodiment of the present disclosure tomodulate the reference voltage V_(REF) based on a single DC-DC powerinductor L_(DC-DC). Common elements between FIGS. 1 and 3 are showntherein with common element numbers and will not be re-described herein.

In a non-limiting example, the voltage modulation circuit 14 includes avoltage amplifier 20 (denoted as “VA”), an offset capacitor C_(OFF), amulti-level charge pump (MCP) 22, the DC-DC power inductor L_(DC-DC),and a switch S_(OFF). The voltage amplifier 20 is configured to generatean initial reference voltage VAMP based on a target voltage V_(TGT),which is received as part of the target signal 18. The offset capacitorC_(OFF) is configured to raise the initial reference voltage V_(AMP) byan offset voltage V_(OFF) to thereby generate the reference voltageV_(REF) (V_(REF)=V_(AMP)+V_(OFF)) at a reference node 24. In thisregard, the voltage amplifier and the offset capacitor C_(OFF) arecollectively responsible for modulating the reference voltage V_(REF) ineach of the voltage generation intervals dT₁-dT_(N). Notably, by usingthe offset capacitor C_(OFF) to raise the initial reference voltageV_(AMP), the initial reference voltage V_(AMP) will be lower than thereference voltage V_(REF), thus helping to improve efficiency of thevoltage amplifier 20.

The MCP 22 is configured to generate a DC voltage V_(DC) as a functionof a battery voltage V_(BAT) and in accordance with a defined dutycycle. In a non-limiting example, the defined duty cycle can also beconfigured via the target signal 18. The DC-DC power inductorL_(DC-DC)-DC is configured to induce a reference current I_(REF) basedon the DC voltage V_(DC) to thereby charge the offset capacitor C_(OFF)to the offset voltage V_(OFF). The switch S_(OFF) may be closed when theoffset capacitor C_(OFF) is charged towards the offset voltage V_(OFF)and opened when the offset capacitor C_(OFF) is charged to the offsetvoltage V_(OFF). In this regard, the offset voltage V_(OFF) is said tobe modulated by the reference current I_(REF).

By modulating the reference voltage V_(REF) and/or the reference currentI_(REF), the voltage modulation circuit 14 further modulates a referencepower P_(REF) (P_(REF)=V_(REF)*I_(REF)) at the reference node 24. Inthis regard, the voltage modulation circuit 14 may also be referred toas a power modulation circuit. In one embodiment, the reference currentI_(REF) can be so generated as a constant current during the voltagegeneration period (T). As such, the voltage modulation circuit 14 canmodulate the reference power P_(REF) by modulating the reference voltageV_(REF).

With reference back to FIG. 1 , the PMIC 10 can include multiple voltageoutputs 26(1)-26(N), each coupled to a respective one of multiple loadcircuits LOAD₁-LOAD_(N) (e.g., power amplifier circuits). The voltagegeneration circuit 12 is coupled to the voltage outputs 26(1)-26(N) andconfigured to concurrently provide the voltages V_(CC1)-V_(CCN) to thevoltage outputs 26(1)-26(N), respectively, during the voltage generationperiod (T). Notably, the load circuits LOAD₁-LOAD_(N) can each act as acurrent source. As such, the load circuits LOAD₁-LOAD_(N) can eachinduce a respective one of multiple load currents I_(LOAD-1)-I_(LOAD-N)in response to receiving a respective one of the voltagesV_(CC1)-V_(CCN). Accordingly, the load circuits LOAD₁-LOAD_(N) will eachconsume a respective one of multiple load powers P_(LOAD-1)-P_(LOAD-N)(P_(LOAD-i)=V_(CCi)*I_(LOAD-i), 1≤i≤N).

The voltage generation circuit 12 may be configured according to anembodiment illustrated in FIG. 4 . FIG. 4 is a schematic diagramproviding an exemplary illustration of the voltage generation circuit 12in the PMIC 10 of FIG. 1 configured according to an embodiment of thepresent disclosure. Common elements between FIGS. 1 and 4 are showntherein with common element numbers and will not be re-described herein.

In a non-limiting example, the voltage generation circuit 12 includesmultiple holding capacitors C_(HOLD-1)-C_(HOLD-N) each coupled between arespective one of the voltage outputs 26(1)-26(N) and a ground (GND).The voltage generation circuit 12 also includes multiple switchedcapacitor-based voltage converters 28(1)-28(N) each configured togenerate a respective one of multiple charging voltagesV_(CHARGE-1)-V_(CHARGE-N) in a respective one of the voltage generationintervals dT₁-dT_(N) based on the reference voltage V_(REF) modulatedduring the respective one of the voltage generation intervalsdT₁-dT_(N). Each of the charging voltages V_(CHARGE-1)-V_(CHARGE-N) cancause a respective one of multiple charge currentsI_(CHARGE-1)-I_(CHARGE-N) to thereby charge a respective one of theholding capacitors C_(HOLD-1)-C_(HOLD-N) to a respective one of thevoltages V_(CC1)-V_(CCN) during a respective one of the voltagegeneration intervals dT₁-dT_(N).

In this regard, the holding capacitors C_(HOLD-1)-C_(HOLD-N) are stillbeing charged sequentially to the voltages V_(CC1)-V_(CCN) during thevoltage generation intervals dT₁-dT_(N). However, each of the holdingcapacitors C_(HOLD-1)-C_(HOLD-N) is so chosen to have a respectivecapacitance that can maintain a respective one of the voltagesV_(CC1)-V_(CCN) for up to the voltage generation period (T). As aresult, the voltages V_(CC1)-V_(CCN) can be simultaneously available atthe voltage outputs 26(1)-26(N) during the voltage generation period(T). Hence, each of the voltage generation intervals dT₁-dT_(N) must belong enough and each of the charge currents I_(CHARGE-1)-I_(CHARGE-N)must be large enough to ensure that a respective one of the holdingcapacitors C_(HOLD-1)-C_(HOLD-N) can be charged to a respective one ofthe voltages V_(CC1)-V_(CCN) during a respective one of the voltagegeneration intervals dT₁-dT_(N).

The switched capacitor-based voltage converters 28(1)-28(N) can beimplemented based on any known switched capacitor-based voltageconverter that does not include a DC-DC power inductor. In oneembodiment, each of the switched capacitor-based voltage converters28(1)-28(N) can be a switched capacitor-based buck voltage converter. Inthis regard, each of the switched capacitor-based voltage converters28(1)-28(N) can operate based on a respective one of multiple conversionratios x₁-x_(N) that is less than or equal to 1 (x₁-x_(N)≤1).Accordingly, each of the switched capacitor-based voltage converters28(1)-28(N) is configured to reduce or pass the reference voltageV_(REF) modulated in a respective one of the voltage generationintervals dT₁-dT_(N) to thereby generate a respective one of the chargevoltages V_(CHARGE-1)-V_(CHARGE-N) that is lower than or equal to thereference voltage V_(REF).

In another embodiment, each of the switched capacitor-based voltageconverters 28(1)-28(N) can be a switched capacitor-based boost voltageconverter. In this regard, each of the switched capacitor-based voltageconverters 28(1)-28(N) can operate based on a respective one of theconversion ratios x₁-x_(N) that is greater than 1 (x₁-x_(N)>1).Accordingly, each of the switched capacitor-based voltage converters28(1)-28(N) is configured to boost the reference voltage V_(REF)modulated in a respective one of the voltage generation intervalsdT₁-dT_(N) to thereby generate a respective one of the charge voltagesV_(CHARGE-1)-V_(CHARGE-N) that is higher than the reference voltageV_(REF). Notably, by boosting the reference V_(REF) to generate thecharge voltages V_(CHARGE-1)-V_(CHARGE-N), the voltage modulationcircuit 14 can be configured to reduce the reference voltage V_(REF)during each of the voltage generation intervals dT₁-dT_(N), thus helpingto improve efficiency of the voltage modulation circuit 14. In addition,the voltage modulation circuit 14 may also reduce the reference currentI_(REF) during each of the voltage generation intervals dT₁-dT_(N), thusmaking it possible to reduce the size of the DC-DC power inductorL_(DC-DC).

In one embodiment, the conversion ratios x₁-x_(N) can be so determinedto be different from one another. Accordingly, the switchedcapacitor-based voltage converters 28(1)-28(N) will each operate basedon a different one of the conversion ratios x₁-x_(N). In anotherembodiment, the conversion ratios x₁-x_(N) can be so determined to beidentical. Accordingly, the switched capacitor-based voltage converters28(1)-28(N) will each operate based on a common conversion ratio. Theconversion ratios x₁-x_(N) can be determined by the control circuit 16or preconfigured in the switched capacitor-based voltage converters28(1)-28(N).

FIGS. 5A and 5B are signal diagrams illustrating exemplary operations ofthe PMIC of FIG. 1 in accordance with embodiments of the presentdisclosure. The illustrations discussed in FIGS. 5A and 5B are based ona set of assumptions. It should be appreciated that the assumptions aremerely made for the convenience of illustration and shall not beconsidered as limiting by any means. Elements in FIGS. 1 and 4 arereferenced in FIGS. 5A and 5B by respective element numbers and will notbe re-described herein.

Herein, the voltage generation circuit 12 is assumed to generate thethree voltages V_(CC1), V_(CC2), and V_(CC3) for the three load circuitsLOAD₁, LOAD₂, and LOAD₃, respectively. In this regard, it is assumedthat there will be three load currents I_(LOAD-1), I_(LOAD-2), andI_(LOAD-3) flowing through the load circuits LOAD₁, LOAD₂, and LOAD₃,respectively.

The voltage generation circuit 12 is also assumed to include the threeswitched capacitor-based voltage converters 28(1), 28(2), and 28(3)(represented by 28(N)) and the three holding capacitors C_(HOLD-1),C_(HOLD-2), and C_(HOLD-3). The holding capacitors C_(HOLD-1),C_(HOLD-2), and C_(HOLD-3) are assumed to be coupled to the threevoltage outputs 26(1), 26(2), and 26(3), respectively. The voltageoutputs 26(1), 26(2), and 26(3) are assumed to be coupled to three loadcircuits LOAD₁, LOAD₂, and LOAD₃, respectively.

Accordingly, the voltage generation period (T) is assumed to be dividedinto three voltage generation intervals dT₁, dT₂, and dT₃(T=dT₁+dT₂+dT₃) for generating the voltages V_(CC1), V_(CC2), andV_(CC3), respectively. In this example, the voltage generation period(T) is assumed to include four time slots (T=4Δt), which are dividedunevenly among the voltage generation intervals dT₁, dT₂, and dT₃. Thevoltage generation interval dT₁ is assumed to include 2 time slots(dT₁=2Δt=1/2T), while the voltage generation intervals dT₂ and dT₃ areassumed to each include 1 time slot (dT₂=dT₃=Δt=1/4 T).

The switched capacitor-based voltage converters 28(1), 28(2), and 28(3)are assumed to operate based on three conversion ratios x₁, x₂, and x₃to convert the reference voltage V_(REF) modulated during the voltagegeneration intervals dT₁, dT₂, and dT₃ into three charging voltagesV_(CHARGE-1), V_(CHARGE-2), and V_(CHARGE-3), respectively. The chargingvoltages V_(CHARGE-1), V_(CHARGE-2), and V_(CHARGE-3), in turn, areassumed to cause three charging currents I_(CHARGE-1), I_(CHARGE-2), andI_(CHARGE-3) for charging the holding capacitors C_(HOLD-1), C_(HOLD-2),and C_(HOLD-3) during the voltage generation intervals dT₁, dT₂, anddT₃, respectively.

With reference to FIG. 5A, in a non-limiting example, the switchedcapacitor-based voltage converters 28(1), 28(2), and 28(3) are eachconfigured to operate as a switched capacitor-based boost voltageconverter based on a common conversion ratio x (x=x₁=x₂=x₃). The loadcurrents I_(LOAD-1), I_(LOAD-2), and I_(LOAD-3) as well as the voltagesV_(CC1), V_(CC2), and V_(CC3) are prestored in the PMIC 10 and thusconsidered known to the control circuit 16. In this example, it isfurther assumed that V_(CC1)=1 Volt (V), V_(CC2)=2 V, V_(CC3)=3 V,I_(LOAD-1)=2 Amp (A), I_(LOAD-2)=1 A, I_(LOAD-3)=1 A, and x=4.

The control circuit 16 may determine each of the charge currentsI_(CHARGE-1), I_(CHARGE-2), and I_(CHARGE-3) as a function of arespective one of the load currents I_(LOAD-1), I_(LOAD-2), andI_(LOAD-3), as expressed in the equations below, for charging theholding capacitors C_(HOLD-1), C_(HOLD-2), and C_(HOLD-3) during thevoltage generation intervals dT₁, dT₂, and dT₃, respectively.

I_(CHARGE-1)=I_(LOAD-1)*(T/dT₁)=4 A

I_(CHARGE-2)=I_(LOAD-2)*(T/dT₂)=4 A

I_(CHARGE-3)=I_(LOAD-3)*(T/dT₃)=4 A

The control circuit 16 can further determine the reference currentI_(REF) during the voltage generation intervals dT₁, dT₂, and dT₃ inaccordance with the equations below.

I_(REF) during dT₁(I_(REF1))=I_(CHARGE-1)/X=4 A/4=1 A

I_(REF) during dT₂ (I_(REF2))=I_(CHARGE-2)/X=4 A/4=1 A

I_(REF) during dT₃ (I_(REF3))=I_(CHARGE-3)/X=4 A/4=1 A

In this regard, the reference current I_(REF) is a constant currentacross the voltage generation intervals dT₁, dT₂, and dT₃. The controlcircuit 16 can further determine the reference voltage V_(REF) duringthe voltage generation intervals dT₁, dT₂, and dT₃ in accordance withthe equations below.

V_(REF) during dT₁(V_(REF1))=x*V_(CC1)=4*1 V=4 V

V_(REF) during dT₂(V_(REF2))=x*V_(CC2)=4*2 V=8 V

V_(REF) during dT₃ (V_(REF3))=x*V_(CC3)=4*4 V=12 V

Accordingly, an average of the reference power P_(REF) as modulated bythe voltage modulation circuit 14 during the voltage generation period(T) can be expressed in the equation below.

$\begin{matrix}{{{AVG}\left( P_{REF} \right)} = {\left( {{{dT}_{1}*V_{{REF}1}*I_{{REF}1}} + {{dT}_{2}*V_{{REF}2}*I_{{REF}2}} + {{dT}_{3}*V_{{REF}3}*I_{{REF}3}}} \right)/T}} \\{= {{\left( {{1/2T*4V*1A} + {1/4T*8V*1A} + {1/4T*12V*1A}} \right)/T} = {7{Watt}(W)}}}\end{matrix}$

Similarly, an average load power AVG(P_(LOAD)) consumed by the loadcircuits LOAD₁, LOAD₂, and LOAD₃ during the voltage generation period(T) can be expressed in the equation below.

$\begin{matrix}{{{AVG}\left( P_{LOAD} \right)} = \left( {{V_{{CC}1}*I_{{LOAD} - 1}} + {V_{{CC}2}*I_{{LOAD} - 2}} + {V_{{CC}3}*I_{{LOAD}3}}} \right)} \\{= {{{1V*2A} + {2V*1A} + {3V*1A}} = {7W}}}\end{matrix}$

With reference to FIG. 5B, the control circuit 16 may control each ofthe switched capacitor-based voltage converters 28(1), 28(2), and 28(3)via a respective one of three control voltages CTRL₁, CTRL₂, and CTR₃.The control circuit 16 may assert the control voltage CTRL₁ prior to orat time T₁ to cause the switched capacitor-based voltage converter 28(1)to charge the holding capacitor C_(HOLD-1), assert the control voltageCTRL₂ prior to or at time T₂ to cause the switched capacitor-basedvoltage converter 28(2) to charge the holding capacitor C_(HOLD-2), andassert the control voltage CTRL₃ prior to or at time T₃ to cause theswitched capacitor-based voltage converter 28(3) to charge the holdingcapacitor C_(HOLD-3). The control circuit 16 may be further configuredto de-assert the control voltage CTRL₁ at or after time T₂, de-assertthe control voltage CTRL₂ at or after time T₃, and de-assert the controlvoltage CTRL₃ at or after time T₄.

With reference back to FIG. 1 , the PMIC 10 may be configured to includea memory circuit 30, which can be a random-access memory (RAM) circuit,a flash storage circuit, or a register bank, as an example. The memorycircuit 30 may be programmed to store the voltages V_(CC1)-V_(CCN) andthe load currents I_(LOAD-1)-I_(LOADN). The memory circuit 30 may befurther programmed to store the conversion ratios x₁-x_(N) of theswitched capacitor-based voltage converters 28(1)-28(N), as shown inFIG. 4 . In a non-limiting example, the memory circuit 30 can beprogrammed via a control bus 32, such as a radio frequency front-end(RFFE) bus or a single-wire serial bus, as an example. Accordingly, thecontrol circuit 16 may retrieve the voltages V_(CC1)-V_(CCN), the loadcurrents I_(LOAD-1)-I_(LOADN), and/or the conversion ratios x₁-x_(N)from the memory circuit 30.

The PMIC may also include multiple feedback circuits FB1-FB_(N), eachconfigured to provide a respective one of a plurality of voltagefeedbacks V_(CC1)-FB-V_(CCN-FB) to the control circuit 16. Notably, eachof the voltage feedbacks V_(CC1-FB)-V_(CCN-FB) can be proportionallyrelated to a respective one of the voltages V_(CC1)-V_(CCN).Accordingly, the control circuit 16 may control the voltage modulationcircuit 14 to adjust the reference voltage V_(REF) during any of thevoltage generation intervals dT₁-dT_(N) based on a respective one of thevoltage feedbacks V_(CC1-FB)-V_(CCN-FB).

Alternative to the voltage generation circuit 12 of FIG. 4 , it is alsopossible to implement the voltage generation circuit 12 based onalternative configurations. In this regard, FIG. 6 is a schematicdiagram of an exemplary voltage generation circuit 34 configuredaccording to another embodiment of the present disclosure. Commonelements between FIGS. 1, 4, and 6 are shown therein with common elementnumbers and will not be re-described herein.

The voltage generation circuit 34 includes multiple hybrid switchcircuits 36(1)-36(N) (denoted as “SW/LDO”). Each of the hybrid switchcircuits 36(1)-36(N) is coupled to a respective one of the holdingcapacitors C_(HOLD-1)-C_(HOLD-N) and can operate either as a switch or alow dropout (LDO) regulator. Specifically, each the hybrid switchcircuits 36(1)-36(N) can provide the reference voltage V_(REF) as arespective one of the charging voltages V_(CHARGE-1)-V_(CHARGE-N)directly to a respective one of the holding capacitorsC_(HOLD-1)-C_(HOLD-N) when operating as the switch. In contrast, whenoperating as the LDO regulator, each of the hybrid switch circuits36(1)-36(N) regulates the reference voltage V_(REF) before providing toa respective one of the holding capacitors C_(HOLD-1)-C_(HOLD-N) as arespective one of the charging voltages V_(CHARGE-1)-V_(CHARGE-N).

In one embodiment, the control circuit 16 may cause the voltagemodulation circuit 14 to modulate the reference voltage V_(REF) in eachof the voltage generation intervals dT₁-dT_(N) to be equal to arespective one of the voltages V_(CC1)-V_(CCN). In this regard, thecontrol circuit 16 may cause each of the hybrid switch circuits36(1)-36(N) to operate as the switch.

In another embodiment, the control circuit 16 may cause the voltagemodulation circuit to modulate the reference voltage in each of thevoltage generation intervals dT₁-dT_(N) to be higher than a respectiveone of the voltages V_(CC1)-V_(CCN). In this regard, the control circuit16 may cause each of the hybrid switch circuits 36(1)-36(N) to operateas the LDO regulator.

The voltage generation circuit 34 may also include a maximum voltagecontrol circuit 38. The maximum voltage control circuit 38 may beconfigured to ensure that the reference voltage V_(REF) is alwaysgreater than or equal to a respective one of the voltagesV_(CC1)-V_(CCN) during a respective one of the voltage generationintervals dT₁-dT_(N) such that none of charging currentsI_(CHARGE-1)-I_(CHARGE-N) can flow back toward the voltage modulationcircuit 14.

With reference back to FIG. 1 , the PMIC 10 may also include anauxiliary voltage generation circuit 40 coupled to the voltagegeneration circuit 12. The auxiliary voltage generation circuit 40 maybe configured generate multiple auxiliary voltages V_(ASS1)-V_(ASSN) toassist in charging the holding capacitors C_(HOLD-1)-C_(HOLD-N) duringthe voltage generation intervals dT₁-dT_(N), respectively. Notably, theauxiliary voltages V_(ASS1)-V_(ASSN) may each cause a respective one ofthe charging currents I_(CHARGE-1)-I_(CHARGE-N) to increase, thushelping to speed up charging of a respective one of the holdingcapacitors C_(HOLD-1)-C_(HOLD-N) during a respective one of the voltagegeneration intervals dT₁-dT_(N). In a non-limiting example, theauxiliary voltage generation circuit 40 may generate each of theauxiliary voltages V_(ASS1)-V_(ASSN) during a respective one of thevoltage generation intervals dT₁-dT_(N) as a function of the referencevoltage V_(REF) modulated during the respective one of the voltagegeneration intervals dT₁-dT_(N).

Those skilled in the art will recognize improvements and modificationsto the preferred embodiments of the present disclosure. All suchimprovements and modifications are considered within the scope of theconcepts disclosed herein and the claims that follow.

1. A power management integrated circuit (PMIC) comprising: a voltagegeneration circuit configured to generate and maintain a plurality ofvoltages during at least one voltage generation period based on areference voltage; a voltage modulation circuit configured to modulatethe reference voltage during the at least one voltage generation period;and a control circuit configured to: divide the at least one voltagegeneration period into a plurality of voltage generation intervals forgenerating the plurality of voltages, respectively; cause the voltagemodulation circuit to modulate the reference voltage to a respectivelevel during each of the plurality of voltage generation intervals; andcause the voltage generation circuit to generate and maintain each ofthe plurality of voltages in a respective one of the plurality ofvoltage generation intervals based on the respective level of thereference voltage modulated during the respective one of the pluralityof voltage generation intervals and maintain each of the plurality ofvoltages till an end of the at least one voltage generation period. 2.The PMIC of claim 1, wherein the voltage generation circuit is furtherconfigured to concurrently provide the plurality of voltages to aplurality of voltage outputs, respectively, during the at least onevoltage generation period.
 3. The PMIC of claim 2, wherein the voltagegeneration circuit comprises a plurality of holding capacitors eachcoupled between a respective one of the plurality of voltage outputs anda ground, the voltage generation circuit is further configured to chargeeach of the plurality of holding capacitors to a respective one of theplurality of voltages during a respective one of the plurality ofvoltage generation intervals.
 4. The PMIC of claim 3, wherein thecontrol circuit is further configured to: divide the at least onevoltage generation period into a plurality of time slots; and determinethe plurality of voltage generation intervals to each include arespective one or more of the plurality of time slots whereby thevoltage generation circuit can charge a respective one of the pluralityof holding capacitors to a respective one of the plurality of voltageswithin a respective one of the plurality of voltage generationintervals.
 5. The PMIC of claim 3, wherein each of the plurality ofholding capacitors is configured to maintain the respective one of theplurality of voltages at the respective one of the plurality of voltageoutputs during the at least one voltage generation period to therebycause the plurality of voltage outputs to output the plurality ofvoltages concurrently during the at least one voltage generation period.6. The PMIC of claim 3, wherein the control circuit is furtherconfigured to: determine a plurality of load currents; determine aplurality of charging currents each as a function of a respective one ofthe plurality of load currents, respectively; and cause the voltagegeneration circuit to generate the plurality of charging currents tocharge the plurality of holding capacitors to the plurality of voltagesduring the plurality of voltage generation intervals, respectively. 7.The PMIC of claim 6, further comprising a memory circuit configured to:store a respective value of each of the plurality of voltages; and storea respective value of each of the plurality of load currents.
 8. ThePMIC of claim 7, wherein the control circuit is further configured toretrieve the plurality of load currents and the plurality of voltagesfrom the memory circuit.
 9. The PMIC of claim 6, wherein the voltagegeneration circuit further comprises a plurality of switchedcapacitor-based voltage converters each coupled to a respective one ofthe plurality of holding capacitors, the plurality of switchedcapacitor-based voltage converters is configured to generate theplurality of charging currents to charge the plurality of holdingcapacitors, respectively.
 10. The PMIC of claim 9, wherein each of theplurality of switched capacitor-based voltage converters is configuredto operate based on a respective one of a plurality of conversion ratiosto convert the reference voltage modulated in each of the plurality ofvoltage generation intervals into a respective one of a plurality ofcharging voltages to thereby cause a respective one of the plurality ofcharging currents to be generated.
 11. The PMIC of claim 10, wherein thecontrol circuit is further configured to cause the voltage modulationcircuit to modulate the reference voltage in each of the plurality ofvoltage generation intervals as a function of a respective one of theplurality of conversion ratios and a respective one of the plurality ofvoltages.
 12. The PMIC of claim 11, wherein the control circuit isfurther configured to: receive a plurality of voltage feedbacks eachcorresponding to a respective one of the plurality of voltages; andcontrol the voltage modulation circuit to adjust the reference voltagein any of the plurality of voltage generation intervals based on arespective one of the plurality of voltage feedbacks.
 13. The PMIC ofclaim 6, wherein the voltage generation circuit further comprises aplurality of hybrid switch circuits each coupled to a respective one ofthe plurality of holding capacitors, each of the plurality of hybridswitch circuits is configured to: operate as a switch to provide thereference voltage directly to a respective one of the plurality ofholding capacitors; and operate as a low dropout (LDO) regulator toregulate the reference voltage before providing the reference voltage tothe respective one of the plurality of holding capacitors.
 14. The PMICof claim 13, wherein the control circuit is further configured to: causethe voltage modulation circuit to modulate the reference voltage in eachof the plurality of voltage generation intervals to be equal to arespective one of the plurality of voltages; and cause each of theplurality of hybrid switch circuits to operate as the switch.
 15. ThePMIC of claim 13, wherein the control circuit is further configured to:cause the voltage modulation circuit to modulate the reference voltagein each of the plurality of voltage generation intervals to be higherthan a respective one of the plurality of voltages; and cause each ofthe plurality of hybrid switch circuits to operate as the LDO regulator.16. The PMIC of claim 3, further comprising an auxiliary voltagegeneration circuit configured to generate a plurality of auxiliaryvoltages to assist in charging the plurality of holding capacitors inthe plurality of voltage generation intervals, respectively.
 17. ThePMIC of claim 1, wherein the voltage modulation circuit comprises: avoltage amplifier configured to generate an initial reference voltagebased on a target voltage; and an offset capacitor configured to raisethe initial reference voltage by an offset voltage to generate thereference voltage.
 18. The PMIC of claim 17, wherein the voltagemodulation circuit further comprises: a multi-level charge pump (MCP)configured to generate a direct current (DC) voltage as a function of abattery voltage in accordance with a defined duty cycle; and a DC to DC(DC-DC) power inductor configured to induce a reference current based onthe DC voltage to thereby charge the offset capacitor to the offsetvoltage.
 19. The PMIC of claim 18, wherein the reference current is aconstant current during the at least one voltage generation period. 20.The PMIC of claim 1, wherein each of the plurality of voltages is aconstant voltage during the at least one voltage generation period.